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SM8702AM
NIPPON PRECISION CIRCUITS INC.
Clock Generator IC
OVERVIEW
The SM8702AM is a clock generator IC that can generate clock signals up to and exceeding 100MHz for personal computer (PC) motherboards. It uses a single 14.318MHz crystal oscillator element and 2 built-in PLLs to simultaneously and independently generate 2 CPU clocks, 6 PCI bus clocks, 2 reference clocks with the same frequency as the crystal element, 48MHz USB interface clock, and 24MHz Super I/O chip clock outputs. It also has 14 outputs that can function as SDRAM clocks by buffering an external input SDRAM clock.
FEATURES
s
PINOUT
pre lim ina
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s
s
s s
s
s
s
s
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Intel(R) Pentium(R) II, Pentium(R) III, and AMD x86compatibles supported 2.5/3.3V CPU clock outputs and IOAPIC clock output 14 x SDRAM clock outputs (3 DIMMs) 2 x CPU clock outputs (60), 66, 75, 83, 95, 100, 103, 112, (124), 133MHz CPU/SDRAM clock frequencies. Values in parentheses are available as mask options. 6 x PCI bus clock outputs (one free-running output) 33MHz or 1/2, 1/3, 1/4 of the CPU clock frequency 2 x reference clock outputs and 1 x IOAPIC clock output 14.318MHz REF/IOAPIC clock frequency 1 x 48MHz USB interface clock output 1 x 24MHz clock output for Super I/O chip I2C serial data bus for frequency/mode output control CPU-stop and PCI-stop functions Spread Spectrum Clock Generator (SSCG) outputs Center spread/Down spread, 0.5% or 1.5% 3.3V (VDD) and 2.5/3.3V (VDDL) supply voltages 48-pin SSOP package (pin compatible with ICS9148-26)
48-pin SSOP (300 mil)
(Top view)
VDD1 REF0 VSS XT XTN VDD2 PCICLK_F/MODE PCICLK0 VSS PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDD2 BUFFERIN VSS SDRAM11/CPU_STOP# SDRAM10/PCI_STOP# VDD3 SDRAM9 SDRAM8 VSS SDATA SCLK
ORDERING INFORMATION
D e vice P ackag e 48-pin SSOP
APPLICATIONS
s
PC motherboards using Intel(R) Pentium(R), Pentium(R) II/III, AMD-K6 devices, and x86 architecture CPUs
Intel(R) and Pentium(R) are registered trademarks of Intel co.. AMD and AMD-K6 are registered trademarks of Advanced Micro Devices, Inc.. I2C Bus is a registered trademark of Philips Electronics N. V..
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1 48
24
25
VDDL1 IOAPIC REF1/FS2 VSS CPUCLK0 CPUCLK1 VDDL2 SDRAM13 SDRAM12 VSS SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 VDD4 48MHz/FS0 24MHz/FS1
SM8702AM
SM8702AM
NIPPON PRECISION CIRCUITS--1
SM8702AM
PACKAGE DIMENSIONS
(Unit: mm)
15.85 0.1
0.3 0.1
0.635
2.59 0.15
2.29 0.05
0.05 0.25 0.03
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NIPPON PRECISION CIRCUITS--2
lim
ina ry
10.285 0.125 7.50 0.05
2 0.20 0.0
0.5 45
0.12 M
0.80 0.1
08
SM8702AM
BLOCK DIAGRAM
(1st PLL)
Unlock Detector XT XTN R-Countor Phase Detector Charge Pump VCO DIV/3 to DIV/6 5 PCICLK_F
N-Countor
BUFFERIN
Buff. Amp.
Unlock Detector
R-Countor
Phase Detector
N-Countor
FS[0:2] MODE
3
lim
I/O Latch ROM I2C Control Logic
SDATA SCLK CPU_STOP# PCI_STOP#
PIN DESCRIPTION
Number 1 Name VDD1 REF0 VSS XT
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- 3.3V supply 2 3 I/O - I Ground 4 5 6 XTN O - VDD2 3.3V supply PCICLK_F O 7 MODE I 8 9 10 PCICLK0 VSS PCICLK1 O - O
I/O
14.318MHz reference clock output Cr ystal oscillator, REF[0:1], 3.3Vline
Cr ystal oscillator input Cr ystal oscillator output PCI clock output buffers, pre-buffer, stop logic, and internal circuit logic supply
PCI bus free-running clock output C P U _ S T OP# (pin 17) and PCI_STOP# (pin 18) mode select pin. M O D E = H I G H : Desktop mode M O D E = L OW : Mobile mode
Mode settings (latch input)
PCI bus clock output Ground (3.3V supply) PCI bus clock output PCI clock output buffers, pre-buffer, stop logic
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Current Source DIV/2 2 SS_CONTROLLER 14 (MS)
PCICLK [0:4]
CPUCLK [0:1]
SDRAM [0:13]
(2nd PLL)
Charge Pump
VCO
DIV/3
48MHz (USB)
Current Source
1/2
24MHz (Super I/O)
2
REF[0:1]
IOAPIC
Function
Notes X T, XTN oscillator, REF[0:1] buffer, stop logic, 3.3V line
NIPPON PRECISION CIRCUITS--3
SM8702AM
Number 11 12 13 14 15 16 17 Name PCICLK2 PCICLK3 PCICLK4 VDD2 BUFFERIN VSS SDRAM11 C P U _ S TO P # SDRAM10 18 19 20 21 22 23 24 25 P C I _ S TO P # VDD3 SDRAM9 SDRAM8 VSS S D ATA SCLK 24MHz FS1 48MHz FS0 I/O - O O - I/O I I/O I/O I/O O O O - I - Function PCI bus clock output PCI bus clock output PCI bus clock output 3.3V supply S D R A M c l o ck input Ground (3.3V supply) S D R A M c l o ck output PCI clock output buffers, pre-buffer, stop logic Input on BUFFERIN is buffered and then output on SDRAM[0:13] S D R A M c l o ck output buffers, pre-buffer, stop logic Notes
CPU clock outputs stop control S D R A M c l o ck output
PCI clock outputs stop control 3.3V supply
S D R A M c l o ck output S D R A M c l o ck output
Ground (3.3V supply) I2 C serial data input I2 C clock input
24MHz clock output
Frequency select 1 (latch input) 48MHz USB clock output
26 27 28 29 30 31 32 33 34 35
lim
I/O - Frequency select 0 (latch input) VDD4 3.3V supply SDRAM7 O S D R A M c l o ck output SDRAM6 VDD3 O - S D R A M c l o ck output 3.3V supply SDRAM5 O S D R A M c l o ck output SDRAM4 VSS O - S D R A M c l o ck output Ground (3.3V supply) SDRAM3 O S D R A M c l o ck output SDRAM2 VDD3 O - S D R A M c l o ck output 3.3V supply SDRAM1 O S D R A M c l o ck output SDRAM0 VSS O - S D R A M c l o ck output Ground (3.3V supply) SDRAM12 O S D R A M c l o ck output SDRAM13 VDDL2 O - S D R A M c l o ck output 2.5/3.3V supply CPU clock output CPU clock output Ground (2.5/3.3V supply) 14.318MHz reference clock output Frequency select 2 (latch input) 14.318MHz IOAPIC clock output 2.5/3.3V supply CPUCLK1 CPUCLK0 VSS REF1 FS2 IOA P I C VDDL1 O O - I/O O -
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36 37 38 39 40 41 42 43 44 45 46 47 48
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S D R A M c l o ck output buffers, pre-buffer, stop logic PLL and internal logic ground, I 2 C interface, 24MHz/48MHz output ground S D R A M c l o ck output buffers, pre-buffer, stop logic S D R A M c l o ck output buffers, pre-buffer, stop logic S D R A M c l o ck output buffers, pre-buffer, stop logic S D R A M c l o ck output buffers, pre-buffer, stop logic CPU clock output buffers, pre-buffer, stop logic CPU clock output buffers, pre-buffer, stop logic IOAPIC output buffer, pre-buffer, stop logic
In mobile mode (MODE = LOW), CPUCLK[0:1] tied LOW w h e n C P U _ S TO P # = L OW .
In mobile mode (MODE = LOW), PCICLK[0:4] tied LOW w h e n P C I _ S TO P # = L OW .
I2 C interface, 24MHz/48MHz output supply, PLL and internal logic supply
NIPPON PRECISION CIRCUITS--4
SM8702AM
SPECIFICATIONS
Absolute Maximum Ratings
VDD:VDD1, VDD2, VDD3, VDD4 VDDL:VDDL1, VDDL2 unless otherwise noted.
VDD (V D D 1 , V D D 2 , V D D 3 , V D D 4 ) Supply voltage range VDDL (V D D L 1 , V D D L 2 ) VSS V IN
Input voltage range Output voltage range Storage temperature range Pow er dissipation
Recommended Operating Conditions
VSS = 0V
P arameter Symbol
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VDD (V D D 1 , V D D 2 , VDD3, VDD4) VDDL (V D D L 1 , V D D L 2 ) T opr C L1 CPUCLK C L2 C L3 PCICLK, SDRAM fR E F
Supply voltages
Operating temperature range
M a x i m um load capacitance
Reference frequency
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NIPPON PRECISION CIRCUITS--5
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-0.3 to 6.0 -0.3 to 6.0 0 - 0.3 to V D D + 0.3 - 0.3 to V D D + 0.3 -55 to 125 0.8 VOUT T stg PD Rating typ Condition min max Excludes internal core, CPU clock and IOAPIC output stages Internal core, CPU clock and IOAPIC output stages 3.135 3.300 3.465 2.375 0 10 20 10 - 2.500 - - - - 14.318 2.625 70 20 30 20 - R E F, 24/48MHz, IOA P I C
P arameter
Symbol
Rating
Unit V V
V V V
C W
Unit
V
V C pF pF pF MHz
SM8702AM
DC Electrical Characteristics
Ta = 0 to 70C, VDD = 3.3V 5%, VDDL = 2.5V 5%, VSS = 0V unless otherwise noted.
Rating P arameter HIGH-level input voltage L O W -level input voltage HIGH-level input current L O W -level input current HIGH-level output voltage L O W -level output voltage HIGH-level output voltage L O W -level output voltage Symbol V IH V IL IIH IIL V OH(3.3V) V OL(3.3V) V OH(2.5V) V OL(2.5V) All pins excl. XT, XTN All pins excl. XT, XTN, SDATA, SCLK S D ATA, SCLK: I2 C interface Condition min 2.0 VSS typ - - - max VDD 0.8 0.7 10 V V A A V V V V Unit
V IH = V D D V IL = 0V
All clock outputs: IO H = -1mA, V D D = 3.135V All clock outputs: IO L = 1mA, V D D = 3.135V
CPUCLK[0:1], IOAPIC: IO H = -1mA, V D D L = 2.375V CPUCLK[0:1], IOAPIC: IO L = 1mA, V D D L = 2.375V CPUCLK[0:1]: V O H = 1.7V P C I C L K _ F, PCICLK[0:4]: V O H = 2.0V
HIGH-level output current
IO H
SDRAM[0:13]: V O H = 2.0V REF[0:1], 24/48MHz: V O H = 2.0V IOAPIC: V O H = 1.7V
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VSS -10 - - - 10 - P C I C L K , S D R A M , R E F, 24/48MHz pins. Also, CPUCLK[0:1] and IOAPIC outputs, when VDDL[1:2] = 3.3V. CPUCLK[0:1] and IOAPIC outputs, when VDDL[1:2] = 2.5V. 2.4 - - - 0.4 - 2.0 - - - 0.4 8.5 23.0 18.7 - 42.6 fO U T = 66.5MHz 18.7 - 42.6 18.7 8.5 11.0 18.7 18.7 18.7 11.0 -10 - fO U T = 66.5MHz - - - - - - - - - - - - - 42.6 23.0 25.3 40.3 40.3 40.3 25.3 10 180 30 20 fO U T = 66.5MHz
mA
lim
CPUCLK[0:1]: V O L = 0.7V P C I C L K _ F, PCICLK[0:4]: V O L = 0.8V IO L SDRAM[0:13]: V O L = 0.8V REF[0:1], 24/48MHz: V O L = 0.8V IOAPIC: V O L = 0.7V IO Z Outputs high impedance C L = 0pF, V D D = 3.465V C L = 0pF, V D D L = 3.465V C L = 0pF, V D D L = 2.625V ID D ID D L 1 ID D L 2
L O W -level output current
mA
Output leakage current
A
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Current consumption
mA
NIPPON PRECISION CIRCUITS--6
SM8702AM
AC Electrical Characteristics
CPU clock characteristics 1 Ta = 0 to 70C, VDD = 3.3V 5%, VDDL = 2.5V 5%, VSS = 0V, fX'tal = 14.318MHz, CL = 20pF unless otherwise noted.
Rating
Output clock rise time 1 Output clock fall Duty cycle Output clock jitter1 time 1
tr tf Dt tjc ts k w
V O L = 0.4V V O H = 2.0V transition time V O H = 2.0V V O L = 0.4V transition time V T = 1.25V
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min - - typ - - max 2.0 2.0 55 45 - 50 - Cycle-to-cycle jitter 250 Between CPUCLK0 and CPUCLK1 - - 250 Supply ON (V D D = 3.3V) until clock reaches specified frequency - - 3 10 - 90 Rating Condition min - - 45 - - typ - - 50 - - max 2.5 2.5 55 250 250 Cycle-to-cycle jitter Between CPUCLK0 and CPUCLK1 Supply ON (V D D = 3.3V) until clock reaches specified frequency - 10 - - 3 60
P arameter
Symbol
Condition
Unit ns ns % ps ps
V T = 1.25V, rising edge V T = 1.25V, rising edge
Output clock skew 1
Clock frequency stabilize time 1 Output impedance 2
tstb ZO
Cold start
ms
V O = 0.5V D D L
1. Design maximum values, not 100% guaranteed. 2. Design estimate values, not 100% guaranteed.
CPU clock characteristics 2
Ta = 0 to 70C, VDD = VDDL = 3.3V 5%, VSS = 0V, fX'tal = 14.318MHz, CL = 20pF unless otherwise noted.
P arameter
lim
Symbol tr tf Dt tjc V T = 1.5V V T = 1.5V, rising edge V T = 1.5V, rising edge ts k w tstb Cold start ZO V O = 0.5V D D L
Unit ns ns % ps ps
Output clock rise time 1 Output clock fall Duty cycle Output clock jitter1 time 1
V O L = 0.4V V O H = 2.4V transition time V O H = 2.4V V O L = 0.4V transition time
Output clock skew 1
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Output impedance 2 1. Design maximum values, not 100% guaranteed. 2. Design estimate values, not 100% guaranteed.
Clock frequency stabilize time 1
ms
NIPPON PRECISION CIRCUITS--7
SM8702AM PCI clock characteristics Ta = 0 to 70C, VDD = 3.3V 5%, VSS = 0V, fX'tal = 14.318MHz, CL = 30pF unless otherwise noted.
Rating P arameter Output clock rise time 1 Output clock fall time 1 Duty cycle Output clock jitter1 Output clock skew 1 Symbol tr tf Dt tjc ts k w Condition min V O L = 0.8V V O H = 2.4V transition time V O H = 2.4V V O L = 0.8V transition time V T = 1.5V - - typ - - max 2.0 2.0 55 ns ns % ps ps Unit
V T = 1.5V, rising edge V T = 1.5V, rising edge
CPU/PCI clock skew 2
thpsk
V T- C P U C L K = 1.25/1.5V, V T- P C I C L K = 1.5V, rising edges Cold start
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45 - 50 - Cycle-to-cycle jitter 250 Between PCI clocks: PCICLK_F and PCICLK[0:4] - - 250 Between CPU and PCI clocks: CPUCLK[0:1] and PCICLK_F/PCICLK[0:4] 1.0 2.2 4.0 Supply ON (V D D = 3.3V) until clock reaches specified frequency - - 3 10 - 60 Rating Condition min - - 40 typ - - 50 max 2.0 2.0 60 3.3V BUFFERIN input clock signal logic level Between SDRAM clocks: SDRAM[0:13] - 200 600 Between BUFFERIN and SDRAM[0:13] - 5.5 7.0 10 - 60
ns
Clock frequency stabilize time 1 Output impedance 3
tstb ZO
ms
V O = 0.5V D D
1. Design maximum values, not 100% guaranteed. 2. CPUCLK and PCICLK r ising edges, V T- C P U C L K = 1.25V (V D D L = 2.5V)/1.5V (V D D L = 3.3V), V T- P C I C L K = 1.5V skew measurement. 3. Design estimate values, not 100% guaranteed.
SDRAM clock characteristics
Ta = 0 to 70C, VDD = VDDL = 3.3V 5%, VSS = 0V, fX'tal = 14.318MHz, CL = 30pF unless otherwise noted.
P arameter Symbol tr tf Unit ns ns %
Output clock rise time 1 Output clock fall Duty cycle 1 time 1
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Input to output propagation delay 2 ,3 tp d Output impedance 3 ZO
Output clock skew 1
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Dt V T = 1.5V, BU F F E R I N input clock signal rise and fall time rate 1V/ns ts k w V T = 1.5V, rising edge, B UFFERIN input clock signal rise and fall time rate 1V/ns V T-BU F F E R I N = 1.5V, V T- S D R A M = 1.5V, rising edges, BUFFERIN input clock signal rise and fall time rate 1V/ns V O = 0.5V D D
V O L = 0.8V V O H = 2.4V transition time V O H = 2.4V V O L = 0.8V transition time
ps
ns
1. Design maximum values, not 100% guaranteed. 2. B U F F E R I N a n d S D R A M r ising edges, V T-BU F F E R I N = 1.5V (logic level = 3.3V), V T- S D R A M = 1.5V delay measurement. 3. Design estimate values, not 100% guaranteed.
NIPPON PRECISION CIRCUITS--8
SM8702AM 24MHz/48MHz, REF[0:1] clock characteristics Ta = 0 to 70C, VDD = 3.3V 5%, VSS = 0V, fX'tal = 14.318MHz, CL = 20pF unless otherwise noted.
Rating P arameter Output clock rise time 1 Output clock fall time 1 Duty cycle 1 Output clock jitter1 Clock frequency stabilize time 1 Output impedance 2 Symbol tr tf Dt tjc tstb ZO Condition min V O L = 0.8V V O H = 2.4V transition time V O H = 2.4V V O L = 0.8V transition time V T = 1.5V - - typ - - max 2.0 2.0 60 ns ns % ps ms Unit
V T = 1.5V, rising edge Cold start
V O = 0.5V D D
1. Design maximum values, not 100% guaranteed. 2. Design estimate values, not 100% guaranteed.
IOAPIC clock characteristics
Ta = 0 to 70C, VDD = 3.3V 5%, VSS = 0V, fX'tal = 14.318MHz, CL = 20pF unless otherwise noted.
Rating typ - - - - 50 250 - - P arameter Symbol Condition
Output clock rise time 1
lim
tr tf Dt tjc V T = 1.5V, V D D L 1 = 3.3V V T = 1.5V, rising edge Cold start tstb ZO V O = 0.5V D D
V O L = 0.8V V O H = 2.4V transition time, V D D L 1 = 3.3V V O L = 0.4V V O H = 2.0V transition time, V D D L 1 = 2.5V
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40 - 50 Absolute jitter 250 - 800 3 Supply ON (V D D = 3.3V) until clock reaches specified frequency - 10 - 60 min - - - - 40 - - 10 max 2.0 2.0 2.0 2.0 60 800 3 90 Absolute jitter Supply ON (V D D = 3.3V) until clock reaches specified frequency
Unit
ns
Output clock fall
time 1
V O H = 2.4V V O L = 0.8V transition time, V D D L 1 = 3.3V V O H = 2.0V V O L = 0.4V transition time, V D D L 1 = 2.5V
ns
Duty cycle 1 Output clock jitter1
% ps ms
Clock frequency stabilize time 1 Output impedance 2
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1. Design maximum values, not 100% guaranteed. 2. Design estimate values, not 100% guaranteed.
NIPPON PRECISION CIRCUITS--9
SM8702AM I2C serial interface electrical characteristics Ta = 0 to 70C, VDD = 3.3V 5%, VSS = 0V, fX'tal = 14.318MHz, CL = 30pF unless otherwise noted.
Rating P arameter Serial clock frequency Serial clock start state hold time Serial clock LOW -level pulsewidth Serial clock HIGH-level pulsewidth Successive start state setup time Data hold time Data input setup time Pulse rise time Pulse fall time Stop state setup time Serial data bus buffer time Bus line load capacitance Symbol fS C L K tH D ; S TA tL O W tH I G H tS U ; S TA tH D ; DAT tS U ; DAT tr tf tS U ; S TO tB U F Cb Condition min I2 C standard mode 0 4.0 4.7 4.0 4.7 0 typ - - - - - max 100 - - - - kHz s s s s s ns ns ns s s pF Unit
SDATA
lim
tf tLOW tr tSU;DAT tf tHD;DAT tHIGH
SCLK
tHD;STA
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NIPPON PRECISION CIRCUITS--10
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I2 C device data - 3.45 - 250 - - - - - 1000 300 - - 4.0 4.7 - - - - 400
tBUF
tHD;STA
tr
tSU;STA
tSU;STO
I 2 C serial data timing
SM8702AM
FUNCTIONAL DESCRIPTION
Mode Setting Overview
There are 2 methods that can be used to set the frequency and clock output start/stop operating modes.
s s
Using external inputs (pins 7, 17, 18, 25, 26, 46) or, Using data read in from an I2C serial interface.
The default state is where the operating state is set by external pin control. Thus, the output frequency can be set by FS[0:2] (pins 25, 26, 46). Note that the SSCG function is OFF in this case. If the I2C serial data byte 0 bit 3 is set to 1, then the output frequency is determined by data using the I2C interface. Then, the Spread Spectrum function (SSCG) can be selected using I2C data. However, if mode settings using I2C data and external pin control conflict or overlap, the mode settings dictated by I2C data have precedence over external pin control. During normal operation, pins 17 and 18 can function as SDRAM clock outputs (desktop mode) or they can function as CPUCLK output stop control and PCICLK output stop control (mobile mode), depending on the state of MODE (pin 7) when power is first applied. In addition to output frequency settings, other operating mode settings which can be controlled by I2C serial data include SSCG operation and mode, and output pin grouping enable/disable switching.
Hardware Frequency Selection
When power is applied, the frequency setting is controlled by FS[0:2] when byte 0 bit 3 is set to 0. Note that if byte 0 bit 3 is set to 1, the frequency is selected by bits 4 to 6 in the same manner as inputs FS0 to FS2.
Inputs FS2 HIGH HIGH HIGH HIGH LOW LOW LOW LOW FS1 HIGH HIGH LOW LOW HIGH HIGH LOW LOW FS0 Output frequency CPUCLK [MHz] 100.2 133
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MODE HIGH LOW Pin 17 Pin 18 Mode SDRAM11 SDRAM10 CPU_STOP# P C I _ S TO P #
Mode and Power Management Inputs
The SM8702AM supports 2 operating modes, desktop mode and mobile mode, selected by MODE (pin 7). If MODE is HIGH when power is first applied, desktop mode is selected. In this mode, pins 17 and 18 function as SDRAM clock outputs, SDRAM11 and SDRAM10, respectively. If MODE is LOW when power is first applied, mobile mode is selected. In this mode, pins 17 and 18 function as the CPU clock (CPUCLK[0:1]) and PCI clock (PCICLK[0:4]) output stop control signal inputs, CPU_STOP# and PCI_STOP#, respectively. This function is used mainly to reduce power consumption.
lim
PCICLK [MHz] 33.4 HIGH LOW 33.2 HIGH LOW 112.1 103 37.3 34.3 HIGH LOW 66.5 33.2 83.3 74.9 41.6 37.4 HIGH LOW 94.7 31.6 Desktop mode Pins 17 and 18 are outputs. Mobile mode Pins 17 and 18 are inputs. NIPPON PRECISION CIRCUITS--11
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SM8702AM
Operating Mode Summary
The state of the various external inputs and outputs in the operating modes is indicated in the following table.
SDRAM11/ C P U _ S TO P # E n a bled (SDRAM output) SDRAM10/ P C I _ S TO P # E n a bled (SDRAM output) VCO P C I C L K _ F, Cr ystal (internal CPUCLK[0:1] PCICLK[0:4] 2 4 M H z / 4 8 M H z , oscillator signal) SDRAM[0:13] E n a bled E n a bled E n a bled E n a bled
MODE MODE = HIGH (desktop mode)
Notes 1
HIGH HIGH ( C P U _ S TOP# input) (PCI_STOP# input)
HIGH LOW ( C P U _ S TOP# input) (PCI_STOP# input) M O D E = L OW (mobile mode) LOW HIGH
( C P U _ S TOP# input) (PCI_STOP# input) LOW LOW ( C P U _ S TOP# input) (PCI_STOP# input)
1. E n a bled = output functions active. Disabled = LOW -level output.
CPU Clock Stop Function
In mobile mode, selected using MODE (pin 7), the CPUCLK[0:1] clock outputs can be stopped by external pin control. The asynchronous stop signal input on CPU_STOP# is sampled internally on the rising edge of the PCI free-running output clock (PCICLK_F).
CPUCLK (internal)
PCICLK (internal)
PCICLK_F (free-running) CPU_STOP# PCI_STOP# (All "H") CPUCLK (external)
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NIPPON PRECISION CIRCUITS--12
lim
When CPU_STOP# goes LOW, the CPU clock outputs (CPUCLK) stop after a delay of 2 to 4 clock cycles. When CPU_STOP# goes HIGH, the CPU clock outputs start after a delay of 2 to 4 clock cycles. The actual start and stop delay varies with the output frequency up to a maximum of 4 CPU clock cycles.
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E n a bled E n a bled E n a bled E n a bled E n a bled E n a bled Disabled E n a bled E n a bled E n a bled Disabled Disabled E n a bled E n a bled Disabled E n a bled E n a bled
Desktop mode. E n a bled Pins 17 and 18 function as outputs.
Mobile mode. Pins 17 and 18 E n a bled function as inputs. Pin 17 = E n a bled C P U _ S T O P # Pin 18 = P C I _ S TO P # E n a bled
SM8702AM
PCI Clock Stop Function
In mobile mode, selected using MODE (pin 7), the PCICLK[0:4] clock outputs can be stopped by external pin control, in the same way as the CPU clock stop function. When PCI_STOP# goes LOW, the PCI clock outputs (PCICLK) stop, and when PCI_STOP# goes HIGH, the PCI clock outputs start. In either case, the PCI_STOP# signal is sampled internally on the rising edge of PCICLK, and the output state transition occurs with 1 PCI clock cycle delay.
CPUCLK (internal) PCICLK (internal) PCICLK_F (free-running) CPU_STOP# (All "H") PCI_STOP# PCICLK (external)
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NIPPON PRECISION CIRCUITS--13
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SM8702AM
I2C Bus Serial Data Format
The format of the I2C serial data on SDATA (pin 23) which is input in sync with the serial data clock on SCLK (pin 24) is shown below. The SM8702AM I2C address is given below.
A6 1
A5 1
In the start sequence, the I2C bus serial data is fed into the clock generator in the following direction. 1. 2. 3. 4. I2C address with R/W# = 0 ACK acknowledge bit Two successive 8-bit dummy command code data words (including ACK acknowledge bit) 8-bit dummy command code (Byte 0 to Byte 5)
The direction of I 2 C Data for Clock Generator 1bit 8bit 1bit 8bit 1bit 8bit I 2 C Addr. A Dummy A Dummy A +R/W# C Command C Command C K Code K Code K D2h
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Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
The data transfer speed is 100k bps (I2C standard mode), with input logic level of 3.3V. When power is first applied, all internal registers are restored to their default state as below.
s
pre
s
Byte0 : default = 0 (bit 0 to bit 3 and bit 7) : default = 1 (bit 4 to bit 6) Byte 1 to Byte 5 : default = 1 (all bits)
ina ry
A4 0 A3 1 A2 0 A1 0 A0 1 R/W# -
R/W# = 0 or 1 1bit A C K 8bit 1bit A C K 8bit 1bit A C K Byte 1 Byte 2 1bit S A T Byte 5 C O K P 8bit Bit 2 Bit 1 Bit 0 NIPPON PRECISION CIRCUITS--14
SM8702AM
I2C Bus Data Bytes
Byte 0: function and frequency select
Bit 7 Function 0: Spread spectrum 1.5% modulation 1: Spread spectrum 0.5% modulation Frequency select bits Bit 6 1 1 6:4 1 1 0 0 0 0 3 2 1 0 Bit 5 1 1 0 0 1 1 0 0 Bit 4 1 0 1 0 1 0 1 0 P o w e r-ON default 0 Notes The spread spectrum accuracy of modulation is not guaranteed.
CPUCLK [MHz] 100.2 133
112.1 103
66.5 83.3 74.9 94.7
0: Hardware frequency select using FS[0:2] 1: I2 C bus serial data frequency select 0: Spread spectrum center spread select 1: Spread spectrum down spread select
0: Normal operating mode (SSCG disabled) 1: Spread spectrum operating mode (SSCG enabled) 0: Normal output mode (running) 1: Three-state output mode
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P o w e r-ON default 1 1 Notes 48MHz USB 1 24MHz (Super I/O) (Reser ved) (Reser ved) (Reser ved) (Reser ved) 1 1 1 1 1 1 C P U C L K 1 e n a ble C P U C L K 0 e n a ble
Byte 1: CPU register
Bit 7 6 5 4 3 2 1 0 Pin number 26 25 - - - -
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43 44 1. 1 = enabled, 0 = disabled
ina ry
PCICLK [MHz] 33.4 33.2 37.3 1 34.3 33.2 41.6 37.4 31.6 0 FS[0:2] are latch inputs 0 0 0
The pow er-ON default for bits 4 to 6 is 1. When bit 3 is set to 1 (I 2 C select), bits 4 to 6 select the frequency in the same write cycle timing.
All outputs are high impedance when bit 0 is set to 1.
Byte 2: PCI register
Bit 7 6 5 4 3 2 1 0 Pin number - 7 - 14 12 11 10 8 P o w e r-ON default 1 1 1 1 1 1 1 1 1 (Reser ved) P C I C L K _ F e n a ble (Reser ved) PCICLK4 enable PCICLK3 enable PCICLK2 enable PCICLK1 enable PCICLK0 enable Notes
1. 1 = enabled, 0 = disabled
NIPPON PRECISION CIRCUITS--15
SM8702AM Byte 3: SDRAM register
Bit 7 6 5 4 3 Pin number - - - - 17, 18 20, 21, 40, 41 28, 29, 31, 32 34, 35, 37, 38 P o w e r-ON default 1 1 1 1 1 1 (Reser ved) (Reser ved) (Reser ved) (Reser ved) Notes
Byte 5: REF/IOAPIC register
Bit 7 6 5 4 3 2 1 0 Pin number - - - P o w e r-ON default 1 1 1 1 (Reser ved) (Reser ved) (Reser ved) Notes
SDRAM[10:11] enable in desktop mode only (MODE = HIGH) SDRAM[8,9,12,13] enable SDRAM[4:7] enable SDRAM[0:3] enable
2 1 0
1 1 1
Byte 4: Reserved register
Bit 7 6 5 4 3 2 1 0 Pin number - - - - - - - - P o w e r-ON default 1 1 1 1 1 1 1 1 1
1. 1 = enabled, 0 = disabled
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698
NP9907AE 1999.07
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(Reser ved) (Reser ved) (Reser ved) (Reser ved) (Reser ved)
NIPPON PRECISION CIRCUITS INC.
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Notes (Reser ved) (Reser ved) (Reser ved) NIPPON PRECISION CIRCUITS--16
1. 1 = enabled, 0 = disabled
ina ry
47 - - 1 1 1 46 2 1 1 1. 1 = enabled, 0 = disabled
IOAPIC enable (Reser ved) (Reser ved)
R E F 1 e n a ble R E F 0 e n a ble

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